It is a purpose of this invention to provide for a wafer scale integration type package for high speed, high input/output (I/O), high density processors, particularly bipolar applications.
Wafer scale integration has been a desired packaging alternative primarily because it has the capability for achieving extremely dense integrated circuit packaging and high circuit speeds. Most of the recent wafer scale integration packaging schemes have not been widely used in industry primarily because of serious yield problems, and costly and complicated redundancy schemes utilized to alleviate the yield problems. Among the reasons for redundancy schemes being counter-productive are that the redundancy required occupies too much area on the chip so that a chip must be made larger to contain the same number of circuits; undesirable delays are introduced into the circuitry for redundancy algorithms; voting circuitry is required and cost is high.
The advantages of wafer scale integration include high packaging density, reduced line capacitance, reduced power dissipation, increased circuit speeds, increased reliability, and reduced package and board costs. It is desirable to achieve these advantages in a high performance package without paying the penalties of low yields and the problems of redundancy. The following references represent attempts at achieving many of the advantages of wafer scale integration by not attempting a total wafer scale integration approach interconnecting a plurality of chips on a wafer.
Chong et al. of Trilogy Systems Corporation in an article "A High Density Multichip Memory Module", published July 1, 1985 by Trilogy Systems Corporation describe an approach of using thin film interconnect technology to package a plurality of VLSI logic and memory chips on a single module as a means of achieving Wafer Scale Integration. The module is based on a thin film copper-polymer technology which displays advantages over multi-layer ceramic technology when comparing interconnect delays and interconnect densities. The module substrate is assembled in a conventional dual in line package upon which are mounted CMOS memory chips and chip capacitors for high frequency bypassing. The package lacks capability for high I/O density and is thus restricted to low performance applications. Thus, it would be inadequate for high speed, high I/O count, bipolar applications.
"The Significance of Wafer Scale Integration in Computer Design", in the IEEE Proceedings of International Conference Computer Design, October 1984 by R. R. Johnson, and U.S. Pat. No. 4,458,297 describe a hybrid interconnection packaging structure for packaging CMOS chips. The structure utilizes a wafer having two levels of silicon wiring separated with amorphous silicon, forming a wiring pattern that can be electrically programmed. Standard commercial chips are wire bonded to the wafer at cells formed by the wiring pattern. Among the limitations of the package are that once a thin film line is used, the remaining line segments that are not used for signal transmission become antenni, adversely affecting electrical performance in the package. There are no means for precise impedance control required for bipolar circuitry having multiple operating voltages. The fact that standard commercial chips, i.e. each chip having a group of internal circuits, drivers and receivers, are utilized in the Johnson package, highlights yet another area in which the state of the art is presently lacking. The drivers and receivers in most cases occupy a substantial portion of the area of each chip (i.e. up to approximately 25-50% or greater depending upon the device technology), and the drivers are a significant user of power (25% and over in many applications, for example, off-chip drivers in many VLSI applications require approximately 5-15 mw each, whereas internal circuits require approximately 0.25-0.75 mw each, while the number of internal circuits usually exceeds the number of off-chip drivers by at least a factor of 10 in most applications), contributing heavily to chip cooling requirements that are increasing as chip and module circuit density are increasing.
The impedance control, coupled noise, delta-I noise, DC drop and capacitive continuity/reflections of the currently available packages are insufficient to have chips interconnected without off-chip drivers and receivers because the noise level in those packages creates an environment wherein the amplification of an off-chip driver is required for a signal to be successfully transferred between two internal circuits, i.e. the noise levels create an environment conducive to false switching. Also, in high performance, high speed VLSI systems, the noise due to reflections is critical because in such high speed systems, the "ringing" effect caused by such reflections causes a delay that cannot be tolerated. Thus, this reflection noise must be substantially reduced. In conventional circuit packaging, utilizing chips, modules, boards, etc., the number of inputs/outputs required as a function of logic circuit density is dictated by Rent's Rule. Rent's Rule is an empirical formula utilized in the industry whenever the total logic circuitry of an integrated circuit containing element (i.e. board, module) is subdivided into smaller units (i.e. chips) within the larger element, and the smaller units are interconnected by wiring the inputs and outputs (I/O) of the smaller units together. Rent's Rule is used in the industry to determine the number of I/O required to fully utilize (or utilize a desired percentage of) the internal circuitry contained in the smaller units (chip, etc.). Rent's Rule is described in various publications such as Hardware and Software Concepts in VLSI, edited by G. Rabbat, 1983, pp. 110-111; "On a Pin Versus Block Relationship for Partitions of Logic Graphs", in IEEE Transactions on Computers, Dec. 1971 by Landman et al. and U.S. Pat. No. 4,398,208. The Rent's Rule equation may be simply stated as follows: EQU I/O required=K[C].sup.R, (EQ. 1)
wherein
K=a constant directly associated with the probability of utilizing the circuitry of the smaller unit. The range of K is between approximately 1.0 and 4.0 for respective probabilities of utilization between 0.1 and 0.9. The value of K is derived from empirical data that is dependent on specific wiring rules used by a circuit packager. PA1 C=the number of logic circuits in the smaller unit. PA1 R=Rent's exponent. Rent's exponent is derived empirically, and depends upon such factors as design efficiency and experience. Typical values of Rent's Exponent are between approximately 0.57 and 0.61.
In currently available chips, wherein the inputs/outputs each operate in conjunction with off-chip drivers and receivers, the number of drivers and receivers required is dictated by Rent's Rule.
In view of the above, a package that could eliminate or greatly reduce the requirement for drivers and receivers on chips would; allow chip area to be utilized for increasing the number and proximity of internal circuits wherein the useful data processing is done, would increase process or speed because of closer proximity of circuits and elimination of driver delays, and also would decrease chip power requirements so that simpler chip cooling means may be utilized.
Such a package would also be capable of emulating a wafer scale integration structure because the elimination or minimization of drivers and receivers would make each group of internal circuits, (each group typically being embodied in a discrete separate semiconductor structure), functionally behave like a group of circuits integrated into a wafer scale integration structure.
Other wafer scale integration designs have been described by Bergendahl et al in "Thick Film Micro Transmission Line Interconnections for Wafer Scale Integration", published in the Proceedings of the 3rd International Symposium on VLSI Science and Technology, 1985. The Bergendahl et al reference describes signal propagation means associated with conventional thin film interconnections on a wafer scale integration level. Bergendahl et al shows how thin film metal lines in the state of the art are unacceptably slow, and describes how thick film lines of certain geometries can achieve superior electrical performance. In addition to not being capable of providing the high densities associated with thin film lines, the reference does not address how to achieve an acceptable power distribution scheme to supply power throughout the wafer scale integration structure. Neither does the reference address the problems that are caused by simultaneous switching noise, coupled noise and achieving the low noise levels required in a wafer scale integration package having substantially no drivers or receivers.
In view of the above, there is a need in the art for an integrated circuit packaging structure which can provide the high circuit density, high performance characteristics of a wafer scale integration structure without suffering from low yields or high redundancy requirements. A need also exists for eulating wafer scale integration performance for high performance bipolar applications, and to reduce circuit power, and consequently reduce cooling requirements. There is also a need in the art for providing an integrated circuit packaging structure that is impedance controlled and has a plurality of interconnected internal circuits, integrated into discrete semiconductor segments, the segments being mounted on an underlying substrate. There is a need for each of the discrete semiconductor segments to have substantially no drivers and receivers or a minimum number thereof (i.e. substantially less than that predicted by Rent's Rule) for signal transmission between each discrete semiconductor segment; (however, the standard number of drivers and receivers per Rent's Rule will still be required for communications between integrated circuits on different underlying substrates). There is also a need in this package to have low inductance, low resistance power distribution while providing large amounts of current to circuits from more than one power supply. The package must have low coupled noise, DC drop, Delta-I noise and matched impedance to lower the noise contributions caused by reflections.
There is also a need for the underlying substrate to substantially match the thermal coefficient of expansion of each discrete semiconductor segment lying thereon.